FIELD OF THE INVENTION
The invention relates to an integrated memory having sense amplifiers disposed on opposite sides of a cell array.
The article, The Charge-Share Modified (CSM) Precharge-Level Architecture for High-Speed and Low-Power Ferroelectric Memory, H. Fujisawa et al., in IEEE Journal of Solid-State Circuits, Vol. 32, No 5, May 1997, page 655 ff. describes a ferroelectric memory (FeRAM or RAM) whose memory cells are of the one-transistor/one-capacitor type. The storage capacitor has a ferroelectric dielectric. The memory cells are disposed at points of intersection of bit lines and word lines. The bit lines are connected to a common sense amplifier through n-channel transistors. In addition, each bit line is connected through a p-channel transistor to a plate potential, to which the electrode of each storage capacitor remote from the selection transistor is also connected. The control connection of the n-channel transistor and of the p-channel transistor in each bit line is connected to a column selection line. Only one of the bit lines is ever accessed at the same time using the column selection lines, the bit line then being conductively connected to the sense amplifier through its n-channel transistor. The other column selection lines remain at a low level, so that the associated bit lines are conductively connected to the plate potential. Although, when one of the word lines is activated, one of the selection transistors in the memory cells on each bit line is turned on, the state stored in the storage capacitors in the unselected bit lines is not affected because the p-channel transistors cause the plate potential to be present on both electrodes of the capacitors. A voltage drop of 0 V across a ferroelectric storage capacitor does not change the polarity of the capacitor. The polarity affects the capacitance of the storage capacitor and corresponds to a particular stored logic state.
In integrated memories, the memory cells disposed at points of intersection of adjacent bit lines and word lines form cohesive cell arrays. If each bit line has to have an appropriate sense amplifier allocated to it, it is beneficial to dispose the sense amplifiers not only on one side of the cell array but alternately on opposite sides of the cell array. Then, there is more space available for configuring the components of the sense amplifiers.
In integrated memories, a plurality of adjacent bit lines is often combined to form a common column having an associated column selection signal. If one of the column selection lines is activated, sense amplifiers on both sides of the cell array are then connected to the bit lines in the appropriate columns and, during read access, amplify the signals read from the addressed memory cells onto these bit lines. To ensure that the surface requirement for the column selection lines in the cell array does not become too large, the column selection lines must be limited in number. On the other hand, limiting the number of column selection lines means that each column selection line has a relatively large number of associated bit lines. Accordingly, during any memory access, a large number of sense amplifiers need to be activated at the same time. Activating more sense amplifiers at the same time increases the power consumption of the integrated memory. In memory cells whose content is destroyed during read access, the sense amplifier is used for writing back the data that has just been read out. Consequently, all the sense amplifiers connected to selected bit lines must be activated normally. Such is the case for DRAMs and FRAMs.